For many applications, such as low power, e.g., in the range of less than 0.1 Watts, it is desirable to increase the magnitude of threshold voltage (Vt) for devices such as nFETs and pFETs. Doing so leads to a decrease of about 10× in sub-threshold leakage for every 80 mV increase in threshold voltage, and thus reduction of power by several orders of magnitude in stand-by situations. In sealed CMOS technologies, this could be a significant part of the overall power dissipation of the chip. Increasing the magnitude of Vt requires additional implant levels, and thus this procedure is applied to increase magnitude of Vt by only a certain fixed amount. However, this cannot be easily accomplished without increasing processing costs associated with obtaining several values of increased threshold voltage.
In conventional methods, increasing the magnitude of device threshold voltage requires additional processing steps in terms of implants and mask levels so that the threshold voltage of a device can be controlled to the desired value.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.